TRAPS-2D: Understanding The Role of the defects to Accomplish high Performance and
Stable Two Dimensional Devices
Overview
Two-dimensional (2D) materials have attracted increasing attention in the last decade. With ultrathin thickness having shown extraordinary optical, electronic and optoelectronic properties, 2D materials are used in semiconductors. Compared to traditional 3D semiconductors, they allow higher integration density. The EU-funded project TRAPS-2D will improve the performance of 2D materials through defect engineering. The aim is to resolve the low performance and to achieve a complementary-metal-oxide (CMOS) technology co-integration. TRAPS-2D will conduct a systematic study of the implications of defect (trap) states on 2D materials. The project’s findings will ultimately result in greatly improved commercial electronic applications.
TMDs Fabrication
We use CVD and ALD techniques to fabricate TMDs (WS2 and MoS2) and graphene layered materials.
Processing
Scalable photo-lithography processes are addressed to perform electronic devices.
Characterization
Structural and Electrical characterization give us more details about the quality and thickness of the synthesized materials and about the electrical performance of the devices.
Project Objectives
# 1
2D devices performance
- Fabrication of 2D layered materials
- Structural Characterization
- Processing/Lithography
- Electrical Characterization
# 2
Defect-engineering
- Defect evaluation
- Origin determination
- How to reduce defects implications
- Alternative applications thanks to defects
# 3
Silicon co-integration
- Schottky barrier suppresion
- Metal contacts engineering
- Thermal budget limitation
- Front-gate selection
Latest News
Synthesis of MoS2 layers and other 2D materials
Chemical vapor depositon of MoS2 on SiO2/Si layers. a) Synthesis process in a two-zone CVD furnace. b) CVD furnace PlanarTech. c) Image of the deposited MoS2 layered material on SiO2 sample. d) Optical image.
Lithography Process
Optical lithography to perform back-gated devices. Scalable process using standard CMOS photo-lithography. Soruce/drain contactas and MoS2 channel are analyzed in SEM (Tescan Vega 3) image.
